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dc.contributor.authorMatallana Fernandez, Asier ORCID
dc.contributor.authorAndreu Larrañaga, Jon ORCID
dc.contributor.authorGárate Añibarro, José Ignacio
dc.contributor.authorAretxabaleta Astoreka, Iker
dc.contributor.authorPlanas Fullaondo, Estefanía ORCID
dc.date.accessioned2024-04-29T17:31:17Z
dc.date.available2024-04-29T17:31:17Z
dc.date.issued2016-12-22
dc.identifier.citationIECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy, 2016 : 3247-3252 (2016)es_ES
dc.identifier.isbn978-1-5090-3474-1
dc.identifier.urihttp://hdl.handle.net/10810/66925
dc.description.abstractIn some power electronic applications, with high current and voltage ranges, discrete devices are not enough unless parallelization techniques are employed. IGBTs are one of the most common and widespread power electronic semiconductors, to make a parallel design with them, either as a discrete devices, dies, individual cells or power modules, it is necessary to know their static and dynamic behaviour. Besides, operation temperature, device parameter tolerances, driver circuit and power layout, as well as different parasitic inductance also affect its performance. The objective of this article is to show and model how all the aforementioned parameters affect the behaviour and performance of a parallelized IGBT, and highlight the design keys for a successful parallelized design.es_ES
dc.description.sponsorshipThis work has been carried out inside the Research and Education Unit UFI11/16 of the UPV/EHU and supported by the Department of Education, Universities and Research of the Basque Country within the fund for research groups IT394-10 and the research program ELKARTEK as the project KT4TRANS (KK-2015/00047). The support of the Ministerio de Economía y Competitividad of Spain within the project DPI2014-53685-C2-2-R and FEDER funds. As well as, the program to support the education of researches of the Basque Country PRE_2015_2_0012.es_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.relationinfo:eu-repo/grantAgreement/MINECO/DPI2014-53685-C2-2-Res_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.subjectparallelizationes_ES
dc.subjectIGBTes_ES
dc.subjectdriveres_ES
dc.subjectlayoutes_ES
dc.subjectbalancees_ES
dc.subjectparasitic inductance (Lσ)es_ES
dc.subjectjunction temperature (Tj)es_ES
dc.subjectstatic and dynamic behavioures_ES
dc.titleAnalysis and modelling of IGBTs parallelization fundamentalses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.rights.holder© 2016 IEEEes_ES
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/7793367es_ES
dc.identifier.doi10.1109/IECON.2016.7793367
dc.departamentoesTecnología electrónicaes_ES
dc.departamentoeuTeknologia elektronikoaes_ES


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