dc.contributor.author | Matallana Fernandez, Asier | |
dc.contributor.author | Andreu Larrañaga, Jon | |
dc.contributor.author | Gárate Añibarro, José Ignacio | |
dc.contributor.author | Aretxabaleta Astoreka, Iker | |
dc.contributor.author | Planas Fullaondo, Estefanía | |
dc.date.accessioned | 2024-04-29T17:31:17Z | |
dc.date.available | 2024-04-29T17:31:17Z | |
dc.date.issued | 2016-12-22 | |
dc.identifier.citation | IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, Florence, Italy, 2016 : 3247-3252 (2016) | es_ES |
dc.identifier.isbn | 978-1-5090-3474-1 | |
dc.identifier.uri | http://hdl.handle.net/10810/66925 | |
dc.description.abstract | In some power electronic applications, with high current and voltage ranges, discrete devices are not enough unless parallelization techniques are employed. IGBTs are one of the most common and widespread power electronic semiconductors, to make a parallel design with them, either as a discrete devices, dies, individual cells or power modules, it is necessary to know their static and dynamic behaviour. Besides, operation temperature, device parameter tolerances, driver circuit and power layout, as well as different parasitic inductance also affect its performance. The objective of this article is to show and model how all the aforementioned parameters affect the behaviour and performance of a parallelized IGBT, and highlight the design keys for a successful parallelized design. | es_ES |
dc.description.sponsorship | This work has been carried out inside the Research and Education Unit UFI11/16 of the UPV/EHU and supported by the Department of Education, Universities and Research of the Basque Country within the fund for research groups IT394-10 and the research program ELKARTEK as the project KT4TRANS (KK-2015/00047). The support of the Ministerio de Economía y Competitividad of Spain within the project DPI2014-53685-C2-2-R and FEDER funds. As well as, the program to support the education of researches of the Basque Country PRE_2015_2_0012. | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | IEEE | es_ES |
dc.relation | info:eu-repo/grantAgreement/MINECO/DPI2014-53685-C2-2-R | es_ES |
dc.rights | info:eu-repo/semantics/openAccess | es_ES |
dc.subject | parallelization | es_ES |
dc.subject | IGBT | es_ES |
dc.subject | driver | es_ES |
dc.subject | layout | es_ES |
dc.subject | balance | es_ES |
dc.subject | parasitic inductance (Lσ) | es_ES |
dc.subject | junction temperature (Tj) | es_ES |
dc.subject | static and dynamic behaviour | es_ES |
dc.title | Analysis and modelling of IGBTs parallelization fundamentals | es_ES |
dc.type | info:eu-repo/semantics/conferenceObject | es_ES |
dc.rights.holder | © 2016 IEEE | es_ES |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/7793367 | es_ES |
dc.identifier.doi | 10.1109/IECON.2016.7793367 | |
dc.departamentoes | Tecnología electrónica | es_ES |
dc.departamentoeu | Teknologia elektronikoa | es_ES |