Functional Verification for SEU Emulation in FPGA Designs

Abstract

In this paper techniques to detect failures in a FPGA are presented and their application to SEU (Single Event Upset) emulation applications is discussed. SEU emulation in FPGAs consists on programming the device with a configuration file that has an erroneous bit, emulating the effect of a SEU. Once the device has been erroneously programmed a verification method is needed to evaluate the criticality of the modified bits. In this work two verification approaches (hardware verification and software verification) are implemented, experimental results are obtained and conclusions are taken.