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dc.contributor.authorPrimicia, Edurne
dc.contributor.authorAstarloa Cuéllar, Armando Fermín
dc.contributor.authorArteaga Pérez, Alejandro
dc.contributor.authorRodriguez, Mikel
dc.contributor.authorVillalta Bustillo, Igor
dc.date.accessioned2024-10-07T17:50:43Z
dc.date.available2024-10-07T17:50:43Z
dc.date.issued2024
dc.identifier.citationXXXIX Conference on Design of Circuits and Integrated Systems, 13-15 November, 2024, Catania, Italyes_ES
dc.identifier.urihttp://hdl.handle.net/10810/69767
dc.descriptionPonencia presentada al DCIS 2024 (noviembre 2024)es_ES
dc.description.abstractThis research presents a SoC implementation of a SpaceWire node, consisting of an open 32-bit RISC-V CPU and an HDL SpaceWire IP core on a European Radiation-Hardened SRAM FPGA (NanoXplore) and a Microchip (Microsemi) FLASH-based FPGA. Both designs were implemented and simulated using the commercial design suites provided by each vendor. Verification of the designs was conducted using two evaluation kits, while the validation of the SoC nodes was performed through conformance tests using SpaceWire commercial testing equipment. SpaceWire is a communication protocol widely adopted in spacecraft for connecting instruments to data processors, mass memory and control processors. Field-Programmable Gate Arrays (FPGAs) are a popular choice for implementing SpaceWire nodes due to their flexibility in meeting the unique requirements of each program or product.es_ES
dc.description.sponsorshipUnion Europea-NextGenerationEU, Cátedras Chip program SOC4SENSING TSI-069100-2023-0004,Research groups of the Basque university system IT1440-22, SOC4CRIS KK-2023/00015 and TSNAERO ZL-2023/00023, Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) IDI-20230111, Fondo Europeo de Desarrollo Regional 2021-2027es_ES
dc.language.isoenges_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.subjectSpaceWire, Spacecraft, On-Board, RISC-V, SRAM FPGA, rad-hardes_ES
dc.subjectSpaceWirees_ES
dc.subjectSpacecrafles_ES
dc.subjecton-boardes_ES
dc.subjectRISC-Ves_ES
dc.subjectSRAM FPGAes_ES
dc.subjectrad-hardes_ES
dc.titleRISC-V based Spacewire Node implemented on European Radiation Hardened FPGA Deviceses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.rights.holder(cc) 2024 Los autores CC BY-NC-ND 4.0es_ES
dc.departamentoesTecnología electrónicaes_ES
dc.departamentoeuTeknologia elektronikoaes_ES


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