RISC-V based Spacewire Node implemented on European Radiation Hardened FPGA Devices

Abstract

This research presents a SoC implementation of a SpaceWire node, consisting of an open 32-bit RISC-V CPU and an HDL SpaceWire IP core on a European Radiation-Hardened SRAM FPGA (NanoXplore) and a Microchip (Microsemi) FLASH-based FPGA. Both designs were implemented and simulated using the commercial design suites provided by each vendor. Verification of the designs was conducted using two evaluation kits, while the validation of the SoC nodes was performed through conformance tests using SpaceWire commercial testing equipment. SpaceWire is a communication protocol widely adopted in spacecraft for connecting instruments to data processors, mass memory and control processors. Field-Programmable Gate Arrays (FPGAs) are a popular choice for implementing SpaceWire nodes due to their flexibility in meeting the unique requirements of each program or product.