Smart Carrier for Scan Chain Emulation of ASIC Prototypes under Test

Abstract

The low and medium complexity SoCs used for sensing and networking in Critical Sectors, like Energy, Industry, Transportation, and A&D, are typically built using mature 65-22nm technologies. The demand for more specialized, secure, and safe devices is growing due to the high specialization demanded by these strategic sectors. In this context, in the R&D project SoC4cris, we are working on a SoC subsystem based on a 32-bit RISC-V for 65-22nm technologies that could be easily adapted to new SoCs oriented to these sectors. The testing stage of the ASIC, once it is manufactured and in prototype stages, is very important. Thus, the main aim of the presented work is to automate this testing stage by developing a flexible and cost-effective scan chain Design-for-Test (DfT) verification method that looks for flexibility and facilitates the testing of the ASIC. Furthermore, this method will allow us to test communication standards typically used in the industry. As the level of integration in digital ICs increases and transistor size decreases, the post-silicon verification of the chips becomes critical. However, the usage of complex Automatic Test Equipment (ATE) is highly expensive, and sometimes very inflexible for little production volumes or multi-project wafers, which complicates its verification. In this paper we propose a low-cost, highly flexible ATE, capable of testing DUTs that integrate Scan Chain as Design-for-Test (DfT) architecture. Our ATE can be used for little production volumes and prototypes where the verification time is not critical, but a exhaustive testing is needed. Together with a SW library based on Python, it is fast and easy to deploy, maintain and modify. Furthermore, it targets a wide range of DUTs as its working frequency can be dynamically modified by user.