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dc.contributor.authorJiménez Verde, Jaime ORCID
dc.contributor.authorMuguira Urtubi, Leire ORCID
dc.contributor.authorBidarte Peraita, Unai ORCID
dc.contributor.authorLargacha, Alejandro ORCID
dc.contributor.authorLázaro Arrotegui, Jesús
dc.date.accessioned2022-08-02T07:39:32Z
dc.date.available2022-08-02T07:39:32Z
dc.date.issued2022
dc.identifier.citationTechnologies 10(3) : (2022) // Article ID 65es_ES
dc.identifier.issn2227-7080
dc.identifier.urihttp://hdl.handle.net/10810/57124
dc.description.abstract[EN] Some complex digital circuits must host various operating systems in a single electronic platform to make real-time and not-real-time tasks compatible or assign different priorities to current applications. For this purpose, some hardware–software techniques—called virtualization—must be integrated to run the operating systems independently, as isolated in different processors: virtual machines. These are monitored and managed by a software tool named hypervisor, which is in charge of allowing each operating system to take control of the hardware resources. Therefore, the hypervisor determines the effectiveness of the system when reacting to events. To measure, estimate or compare the performance of different ways to configure the virtualization, our research team has designed and implemented a specific testbench: an electronic system, based on a complex System on Chip with a processing system and programmable logic, to configure the hardware–software partition and show merit figures, to evaluate the performance of the different options, a field that has received insufficient attention so far. In this way, the fabric of the Field Programmable Gate Array (FPGA) can be exploited for measurements and instrumentation. The platform has been validated with two hypervisors, Xen and Jailhouse, in a multiprocessor System-on-Chip, by executing real-time operating systems and application programs in different contexts.es_ES
dc.description.sponsorshipThis work has been supported by the Basque Government within the project HAZITEK ZE-2020/00022 as well as the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264 and FEDER fundses_ES
dc.language.isoenges_ES
dc.publisherMDPIes_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/
dc.subjectvirtualizationes_ES
dc.subjecthypervisores_ES
dc.subjectvirtual machineses_ES
dc.subjectmulti processores_ES
dc.subjectmulti-operating-systemes_ES
dc.titleSpecific Electronic Platform to Test the Influence of Hypervisors on the Performance of Embedded Systemses_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.date.updated2022-06-23T12:20:45Z
dc.rights.holder© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).es_ES
dc.relation.publisherversionhttps://www.mdpi.com/2227-7080/10/3/65es_ES
dc.identifier.doi10.3390/technologies10030065
dc.departamentoesTecnología electrónica
dc.departamentoeuTeknologia elektronikoa


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© 2022 by the authors.
Licensee MDPI, Basel, Switzerland.
This article is an open access article
distributed under the terms and
conditions of the Creative Commons
Attribution (CC BY) license (https://
creativecommons.org/licenses/by/
4.0/).
Except where otherwise noted, this item's license is described as © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).