Encryption AXI Transaction Core for Enhanced FPGA Security
dc.contributor.author | Lázaro Arrotegui, Jesús | |
dc.contributor.author | Astarloa Cuéllar, Armando Fermín | |
dc.contributor.author | Muguira Urtubi, Leire | |
dc.contributor.author | Bidarte Peraita, Unai | |
dc.contributor.author | Jiménez Verde, Jaime | |
dc.date.accessioned | 2022-11-04T13:52:31Z | |
dc.date.available | 2022-11-04T13:52:31Z | |
dc.date.issued | 2022-10-18 | |
dc.identifier.citation | Electronics 11(20) : (2022) // Article ID 3361 | es_ES |
dc.identifier.issn | 2079-9292 | |
dc.identifier.uri | http://hdl.handle.net/10810/58253 | |
dc.description.abstract | The current hot topic in cyber-security is not constrained to software layers. As attacks on electronic circuits have become more usual and dangerous, hardening digital System-on-Chips has become crucial. This article presents a novel electronic core to encrypt and decrypt data between two digital modules through an Advanced eXtensible Interface (AXI) connection. The core is compatible with AXI and is based on a Trivium stream cipher. Its implementation has been tested on a Zynq platform. The core prevents unauthorized data extraction by encrypting data on the fly. In addition, it takes up a small area—242 LUTs—and, as the core’s AXI to AXI path is fully combinational, it does not interfere with the system’s overall performance, with a maximum AXI clock frequency of 175 MHz. | es_ES |
dc.description.sponsorship | This work has been supported within the fund for research groups of the Basque university system IT1440-22 by the Department of Education and within the PILAR ZE-2020/00022 and COMMUTE ZE-2021/00931 projects by the Hazitek program, both of the Basque Government, the latter also by the Ministerio de Ciencia e Innovación of Spain through the Centro para el Desarrollo Tecnológico Industrial (CDTI) within the project IDI-20201264 and IDI-20220543 and through the Fondo Europeo de Desarrollo Regional 2014–2020 (FEDER funds). | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | MDPI | es_ES |
dc.rights | info:eu-repo/semantics/openAccess | es_ES |
dc.rights.uri | http://creativecommons.org/licenses/by/4.0/ | |
dc.subject | communication system security | es_ES |
dc.subject | data buses | es_ES |
dc.subject | data security | es_ES |
dc.subject | field-programmable gate arrays | es_ES |
dc.subject | hardware security | es_ES |
dc.title | Encryption AXI Transaction Core for Enhanced FPGA Security | es_ES |
dc.type | info:eu-repo/semantics/article | es_ES |
dc.date.updated | 2022-10-26T11:08:20Z | |
dc.rights.holder | © 2022 by the authors.Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/ 4.0/). | es_ES |
dc.relation.publisherversion | https://www.mdpi.com/2079-9292/11/20/3361 | es_ES |
dc.identifier.doi | 10.3390/electronics11203361 | |
dc.departamentoes | Tecnología electrónica | |
dc.departamentoeu | Teknologia elektronikoa |
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Except where otherwise noted, this item's license is described as © 2022 by the authors.Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/ 4.0/).