dc.contributor.author | Bildosola Agirregomezkorta, Iñaki ![ORCID](/themes/Mirage2//images/orcid_16x16.png) | es |
dc.contributor.author | Martínez Corral, Unai ![ORCID](/themes/Mirage2//images/orcid_16x16.png) | es |
dc.contributor.author | Basterrechea Oyarzabal, Koldobika | es |
dc.date.accessioned | 2014-09-16T17:43:31Z | es |
dc.date.accessioned | 2014-10-08T10:01:20Z | |
dc.date.available | 2014-09-16T17:43:31Z | es |
dc.date.available | 2014-10-08T10:01:20Z | |
dc.date.issued | 2014-06-18 | es |
dc.identifier.citation | 25th International Conference on Application-specific Systems, Architectures and Processors (ASAP 2014, Zurich | es |
dc.identifier.uri | http://hdl.handle.net/10810/13397 | es |
dc.description.abstract | Singular Value Decomposition (SVD) is a key linear algebraic operation in many scientific and engineering applications. In particular, many computational intelligence systems rely on machine learning methods involving high dimensionality datasets that have to be fast processed for real-time adaptability. In this paper we describe a practical FPGA (Field Programmable Gate Array) implementation of a SVD processor for accelerating the solution of large LSE problems. The design approach has been comprehensive, from the algorithmic refinement to the numerical analysis to the customization for an efficient hardware realization. The processing scheme rests on an adaptive vector rotation evaluator for error regularization that enhances convergence speed with no penalty on the solution accuracy. The proposed architecture, which follows a data transfer scheme, is scalable and based on the interconnection of simple rotations units, which allows for a trade-off between occupied area and processing acceleration in the final implementation. This permits
the SVD processor to be implemented both on low-cost and highend FPGAs, according to the final application requirements. | es |
dc.description.sponsorship | This work was supported by the Spanish Ministry of Economy and Competitiveness, and European FEDER funds (grant TEC2010-15388), and by the Basque Government (grants IT733-13, S-PC12UN016, and S-PC13UN034). | es |
dc.language.iso | eng | es |
dc.publisher | Institute of Electrical and Electronic Engineers (IEEE) | es |
dc.rights | info:eu-repo/semantics/openAccess | es |
dc.subject | Singular Value Decomposition (SVD) | es |
dc.subject | adaptive threshold | es |
dc.subject | selectable accuracy | es |
dc.subject | scalable architecture | es |
dc.subject | Field Programmable Gate Array (FPGA) | es |
dc.subject | error regularization | es |
dc.subject | high dimensionality datasets | es |
dc.subject | linear algebraic operation | es |
dc.title | Adaptive Scalable SVD Unit for Fast Processing of Large LSE Problems | es |
dc.type | info:eu-repo/semantics/article | es |
dc.rights.holder | (c) 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained
for all other users, including reprinting/republishing this material for advertising or promotional
purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any
copyrighted components of this work in other works. | es |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6868625 | es |
dc.identifier.doi | 10.1109/ASAP.2014.6868625 | es |
dc.departamentoes | Tecnología electrónica | es_ES |
dc.departamentoes | Ingeniería de sistemas y automática | es_ES |
dc.departamentoeu | Teknologia elektronikoa | es_ES |
dc.departamentoeu | Sistemen ingeniaritza eta automatika | es_ES |